The new SiC-LV100 SiC-MOSFET module features an optimized structure that tackles the challenges of high current density and high-speed switching.
This article is published by EEPower as part of an exclusive digital content partnership with Bodo’s Power Systems.
Article co-authored by Tetsuo Yamashita, Mitsubishi Electric, Fukuoka, Japan
As the share of renewable energy continues to grow, the demand for large capacity, high power density, and greater efficiency is increasing. Mitsubishi Electric is developing a power module utilizing SiC-MOSFET devices to meet these requirements.
Image used courtesy of Adobe Stock
SiC-MOSFET devices show high efficiency with low power losses by high-speed switching. The power module consists of only SiC-MOSFETs without separate diodes by utilizing the body-diode built-in the MOSFET in large capacity housing “LV100”.
This configuration realizes high current density and a current rating of 1,800 A (under development). Besides, the optimized voltage rating for excellent LTDS performance (, which matches the optimal solution for 1,000 VAC and 1,500 VDC systems as the recent link voltage standard for renewable applications.
High current density leads to significant heat generation, demanding excellent thermal performance for effective heat dissipation. SiC-LV100 consists of high thermal conductive components like Aluminum Nitride (AlN) substrate.
On the other hand, such high current density and high-speed switching could result in lower module robustness. This module integrates higher number of parallel-connected MOSFET chips than conventional modules with separated transistors and diodes chips.
However, this setup makes it challenging to maintain uniform current distribution among all chips. Parallel-connected MOSFETs, which are designed to realize high-speed switching with low capacitance, can lead to gate voltage oscillation, potentially resulting in unexpected failures.
Accordingly, the design incorporates appropriate components and a well-optimized layout to ensure stable operation. The LV100 module shows high performance by SiC-MOSFETs, along with sufficient capability provided by its improved structural design.
Module Configuration
Mitsubishi Electric adopted Solid Cover (SLC) technology with insulating metal baseplate and resin encapsulation for the 7th generation Si-IGBT modules, such as LV100 housing [1].
This packaging technology shows competent thermal resistance and an isolation voltage of 4 kV. Furthermore, it improves thermal cycling capability by eliminating the solder layer beneath the substrate. This is achieved by using an insulated metal baseplate (IMB) that integrates the insulating layer, circuit pattern, and baseplate as a single component. Electrical isolation from the baseplate is maintained by the resin-based insulating layer.
However, the new SiC-LV100 adopts a high thermal performance AlN substrate and cupper baseplate e with encapsulating gel to make full use of SiC-MOSFETs.
The following are the main features of SiC-MOSFETs:
- High thermal conductivity, which enables efficient heat dissipation.
- Wide bandgap energy, allowing stable operation at elevated temperatures.
- High breakdown electric field, enabling a thinner drift layer and reduced on-resistance.
SiC-MOSFET enables higher current density than Si-IGBT due to these properties. As a result, high current density is a key selling point for SiC power modules. The LV100 module has been optimized for high current density with excellent thermal dissipation capability.
Table 1. Configurations of Si-LV100 and SiC-LV100. Image used courtesy of Bodo’s Power Systems [PDF]
1. Utilizing the Body-Diode Built-in the MOSFET
Only SiC-MOSFET devices are mounted on the SiC-LV100 module. The MOSFETs include intrinsic body-diodes, which function as freewheeling diodes for commutation during dead time operation. The MOSFET is bidirectional and can be turn-on to reduce conduction loss on freewheeling phase. The SiC-MOSFET naturally combines transistor and diode functions within a single device, leading to more constant heat generation and improved thermal dissipation.
Moreover, the required mounting area for SiC-MOSFETs is smaller than that of a separate transistor-diode pair. As a result, more devices can be mounted on a single module, thereby increasing the current density of the module.
2. Ceramic Insulation Structure with AlN substrate
Aluminum nitride (AlN)-based substrates are known for their excellent heat dissipation performance. In the SLC structure adopted in the Si-LV100 modules, the mounting area on the insulating metal baseplate can be increased compared to the conventional ceramic insulation structure [1].
However, since SiC devices achieve high current density per chip, mounting area is unlikely to become a bottleneck in thermal design or output power. Instead, improving heat dissipation becomes a more critical consideration. The use of AlN substrates further enhances the module’s thermal performance.
Figure 1 shows a thermal analysis comparison between the SLC structure and the ceramic insulation structure with an AlN substrate, assuming the SiC-LV100 module. As can be seen from the figure, the ceramic insulation structure with an AlN substrate achieves a lower junction temperature (Tvj) in the simulation. Although the layout, chip size, and number of chips differ, the total mounting area was equal in both cases, minimizing the impact on thermal performance.
The images show the differences in internal layouts, chip size and chip count. However, the total chip mounting area was the same, so these differences have negligible impact on thermal performance.
Figure 2 shows the impact on the thermal resistances. Rth(j-c), is defined from the chips to the case and Rth(c-s) is defined from the case to the heatsink. Thermal resistance from the chips to the heatsink is 11 % lower in the ceramic insulation structure with a AlN substrate compared to the SLC structure.
Figure 1. Temperature Distribution Comparison. Image used courtesy of Bodo’s Power Systems [PDF]
Figure 2. Thermal Resistance Comparison. Image used courtesy of Bodo’s Power Systems [PDF]
Concerns with High Current Density and High-Speed Switching
SiC devices generally exhibit high-speed switching and low switching losses. Especially the SiC-LV100 adopted 2nd generation planar SiC-MOSFETs because it can reduce the capacitance and achieve the high-speed switching [2]. On the other hand, this module includes more parallel devices internally than conventional Si-IGBT modules to achieve higher current density. These features may lead to the following risks.
- Uneven current distribution
- Gate voltage oscillation
Parallel chips exhibit differences in impedance in both the gate and main current circuits. These impedance differences make it difficult to maintain balanced collector current among the individual parallel chips.
Current concentration in specific chips may result in rapid current change (di/dt), which can degrade the module robustness due to surge voltage caused by stray inductance (Ls) and di/dt. In addition, a parallel chip layout often induces gate voltage oscillation, which becomes more pronounced as the number of parallel chips increases and the switching speed becomes higher [3].
This oscillation occurs because each chip forms an LC-resonant circuit, and these multiple LC circuits interfere with one another. To suppress gate voltage oscillation, the SiC-LV100 circuit layout is optimized to minimize impedance differences among the parallel chips.
Figure 3 compares source inductance between parallel chips for two different layout types. In the bottom graph of Figure 3, the source inductance of each of the six chips, based on analysis, is shown. The optimal layout minimizes the source inductance of each chip, and the variation is reduced by approximately 70 % compared to the conventional layout.
Figure 3. Models and Results of Source Inductance Analysis. Image used courtesy of Bodo’s Power Systems [PDF]
Figure 4 shows a comparison of current distribution among parallel chips along the X axis. The optimal layout improves current balance across the chips and reduces the peak di/dt in the parallel configuration. This optimal design addresses the two risks mentioned above and ensures stable module performance.
Figure 4. Models and results for current flow analysis between chips. Image used courtesy of Bodo’s Power Systems [PDF]
Performance Comparison
The SiC-LV100, which targets a voltage rating of 2,500 V, is designed for 1,500 Vdc link voltage applications using a 2-level topology. This module features an on-resistance of RDS(on) = 1.9 mΩ (under development) at Tvj = 150 °C.
Table 2 and Figure 5 present the performance comparison with two Si-IGBT-based solutions that are also suitable for 1,500 Vdc systems: a 7th generation 1,200V Si-IGBT module using a 3-level A-NPC topology, and a 7th generation 2,000V Si-IGBT module using a 2-level topology. In this comparison, the SiC-LV100 achieves more than a 100 % increase in output current compared to Si-IGBT module solutions.
Table 2. Summary of Performance Comparison (Other conditions: VDC = 1500 V, Power factor = 1, and a modulation index = 0.7). Image used courtesy of Bodo’s Power Systems [PDF]
Figure 5. Correlation between Io and Tvj. Image used courtesy of Bodo’s Power Systems [PDF]
Conclusion
The new SiC-LV100, targets a voltage rating of 2,500 V, is developed for 1,000 VAC / 1,500 VDC 2-level inverters systems in renewable applications. In addition to the high thermal conductivity of SiC itself, this module employs the ceramic insulation structure with an AlN substrate to achieve both excellent heat dissipation and high current density.
With this configuration, the thermal resistance from the chips to the heatsink becomes 11 % lower compared to the SLC structure adopted in the Si-LV100 modules. However, the high current density and high-speed switching introduce two key challenges: uneven current distribution and gate voltage oscillation. To address these issues, the module’s internal layout has been optimized to minimize the source inductance of each chip.
In comparison with conventional 7th generation LV100 modules using both 2-level and 3-level A-NPC topology, the SiCLV100 achieves over a 100 % increase in output current. By taking advantage of SiC-MOSFETs and an optimized structural design, the SiC-LV100 demonstrates outstanding performance and enhanced robustness.
References
[1] Takuya Takahashi et. al., “A 1700V-IGBT module and IPM with new insulated metal baseplate (IMB) featuring enhanced isolation properties and thermal conductivity”, PCIM Europe 2016.
[2] Kenichi Hamano et al., “2nd generation High performance 4HSiC MOSFETs with 1.7 kV rating for high power applications”, PCIM Europe 2019
[3] Florian Sawallich et al., “Inter-chip Oscillation of paralleled SiC MOSFETs”, PCIM Europe 2023
This article originally appeared in Bodo’s Power Systems [PDF] magazine and is co-authored by Akiyoshi Masuda, Mitsubishi Electric Europe B.V., Ratingen, Germany and Tetsuo Yamashita, Mitsubishi Electric, Fukuoka, Japan
